Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization
In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model.Solving data- and task-parallelism is crucial during COUNTRY PEACH PASSION this process.For data parallelism, a RISC-V Simulink library written in ve